1. Technical Field
The present invention relates to a system and method for efficiently testing cache congruence classes during processor design verification and validation. More particularly, the present invention relates to a system and method for minimizing test case build time by using a single test case to test each sector within multiple congruence classes.
2. Description of the Related Art
Processor testing tools exist whose goal is to generate the most stressful test case for a processor. In theory, the generated test case should provide maximum test coverage and should be interesting enough to stress various timing scenarios on the processor. The whole technology of these tools sits in the logic of building these test cases. Verifying and validating a processor using test cases typically includes three stages, which are 1) a test case build stage, 2) a test case execution stage, and 3) a validation and verification stage.
A processor typically includes one or more caches that also require validation and verification, which are small and fast memories (relative to main memory) that are physically close to the processor's core. Since caches are much smaller than the main memory, only the most recently used memory blocks or lines reside in the cache at any given time. As a result, processor designs include a mapping algorithm that maps multiple addresses to different blocks in a cache. One such mapping algorithm divides effective addresses into three sections, which are a tag, and index, and an offset. The tag bits identify a block location within the cache. The index bits identify a cache line within the cache, and the offset bits identify a byte location within the cache line.
The index is also referred to as “congruence class.” In a configuration where the cache is an n-way associative cache, each index includes ‘n’ lines, such as a 512 KB, 8-way set associative L2 cache. As such, each congruence class includes ‘n’ ways. When a processor indexes into the cache, the processor performs a linear search to locate the exact way or line, and then uses the offset bits to locate the particular byte to access. A challenge found, however, is that a large amount of test cases are required in order to fully test each of the cache's congruence classes/ways. Unfortunately, this consumes a large amount of build time, which leaves less time available for test case execution, validation and verification.
In addition, a cache's contents are typically divided into sectors that have corresponding parity bits. Calculating parity for a sector is implementation dependent, and typically commences once a test case accesses the sector. A challenge found, however, is creating a test case that frequently transitions bits in each sector such that a cache parity error is detected in the shortest possible time.
What is needed, therefore, is a system and method for efficiently testing each congruence class/way within a cache while sufficiently accessing each sector in order to quickly detect cache parity errors.